×

You are using an outdated browser Internet Explorer. It does not support some functions of the site.

Recommend that you install one of the following browsers: Firefox, Opera or Chrome.

Contacts:

+7 961 270-60-01
ivdon3@bk.ru

  • The hardware implementation of the modulo operation for input data of high bit width on the basis of reduction and correction blocks

    The operation of finding the remainder of division is an arithmetic operation that plays a big role in number theory. The most important role this operation has in the design of devices using, modular arithmetic. Modular arithmetic has high parallelism and is often used with high-dimensional data to speed up computations. When working with modular arithmetic, data of large dimensions (about 128-512 bits) are often used. To find modular representation of data, effective way is needed to find the remainder from the division of multi-digit numbers by the corresponding set of moduli. The article explores the methods for constructing devices for finding the remainder of the division, for large dimensions of input data, in which the divisor p - is a constant and is known at the device design stage. The options for implementing such devices are investigated, their optimal parameters are determined, and the delay and area compared with the Verilog operation "%", both in the VLSI and in the FPGA synthesis.

    Keywords: residue number system, remainder of division, modulo operation, cad

  • Synchronization system in circuits with a high degree of integration

    The crosstalk level increases with increasing degree of circuit integration. At the same time, requirements to their noise immunity increase. The increase in the amplitude of the pulse signals is a simple and effective method to improve noise immunity. The article discusses the synchronization system with the global distribution of low-voltage clock signal and a local increase in the amplitude using drivers with increasing voltage. Proposed technical solutions allow to set the amplitude of the clock signal individually for each functional unit.

    Keywords: synchronization, noise immunity, clock signal drivers, amplitude increase, source and power rail reduction

  • The analysis of constructive and technological restrictions in design of the avalanche photo diodes, working in a photon-counting mode

    Theoretical analysis of constructive and technological restrictions in the avalanche photodiode structure for photon-counting mode is made in this work. It is shown that critical parameters are load resistance and a time constant of a photodiode internal capacity recharge. For decreasing this time constant one needs size restriction of separate section of the photodiode and association of several such sections on a crystal together with registration schemes.

    Keywords: Avalanche photodiode, Mode of the account of photons, Constructive-technological restrictions, Model of avalanche breakdown