In this article, the evaluation of the effect of the trace elements on the reliability of the design of the combinational circuit in the field-programmable gate array (FPGA) basis is researched. An evaluation of the reliability of combinational circuits in the basis of three-input FPGA cells, as well as three-input FPGA cells, taking into account the trace elements, is given. Proposed methods for evaluate the reliability of the project at various stages of the development of fault-tolerance projects in the FPGA basis. The use of these methods allows the design of combinational circuits of increased reliability in the basis of reconfigurable integrated circuits without built-in reliability features.

Keywords: reliability, evaluation fault tolerance, combinational circuit, FPGA, fault injection

The operation of finding the remainder of division is an arithmetic operation that plays a big role in number theory. The most important role this operation has in the design of devices using, modular arithmetic. Modular arithmetic has high parallelism and is often used with high-dimensional data to speed up computations. When working with modular arithmetic, data of large dimensions (about 128-512 bits) are often used. To find modular representation of data, effective way is needed to find the remainder from the division of multi-digit numbers by the corresponding set of moduli. The article explores the methods for constructing devices for finding the remainder of the division, for large dimensions of input data, in which the divisor p - is a constant and is known at the device design stage. The options for implementing such devices are investigated, their optimal parameters are determined, and the delay and area compared with the Verilog operation "%", both in the VLSI and in the FPGA synthesis.

Keywords: residue number system, remainder of division, modulo operation, cad