At present, field programmable gate arrays are in high demand at design of automation and control devices. The basis of field programmable gate array logic element is the generator of functions of N variables, which is often called Look-up Table (LUT). LUT is based on a multiplexer and constructed as a tree of elementary multiplexers 2:1. LUT tuning is realizing by loading the constants to the inputs of static random access memory. At the article the simplest LUT with one variable is analyzed in detail. But the existing logical element has a deficiency. It is that M LUTs are required to implement M logic functions. In the CMOS transistors used in the LUT, drain nodes and sources are equivalent which allows reversing the signals. Based on this, there is proposed the LUT decoder (DC-LUT). A detailed description of the DC-LUT is provided at the article. The implementation of DC-LUT with a large number of variables is also considered. The proposed structure of DC-LUT allows implementing a system of logical functions that depend on conjunctions of a perfect disjunctive normal form more effective, in contrast with the existing solution.

Keywords: field-programmable gate array, look-up table, the system of logical functions, perfect disjunctive normal form

The use of a self-timed look up table is explored in order to realize systems of logical functions. The self-timed look up table is modeled in its operational and spacer stages in NI Multisim 10 electronic schematic capture and simulation program by National Instruments Electronics Workbench Group. Efficiency of technical solution is confirmed. Systems of logical functions are described in a principal disjunctive normal form. The problems are set for further research.

Keywords: self-timed curcuit, CMOS transistor, paraphase channel, logical functional system, look up table (LUT), inverter, operating stage, spacer stage, logical element, principal disjunctive normal form (PDNF)

In this paper a modification of logic element DC LUT FPGA is proposed for the purpose of the acceleration of diagnostics. Simulation of proposed modification was performed in the system NI Multisim 10 by National Instruments Electronics Workbench Group. Evaluation of hardware costs is also given.

Keywords: logic element, DC LUT, FPGA, diagnosis, reliability